| 61. | Which of the following 8085 microprocessor hardware interrupt has the lowest priority? |
| a. | RST 6.5 |
| b. | RST 7.5 |
| c. | TRAP |
| d. | INTR |
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Answer: (d).INTR
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| 62. | A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes? |
| a. | 0.64 |
| b. | 0.96 |
| c. | 2.00 |
| d. | 0.32 |
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Answer: (d).0.32
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| 63. | A DMA controller transfers 32-bit words to memory using cycle Stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer? |
| a. | 0.06% |
| b. | 0.12% |
| c. | 1.2% |
| d. | 2.5% |
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Answer: (b).0.12%
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| 64. | A CPU handles interrupt by executing interrupt service subroutine................. |
| a. | by checking interrupt register after execution of each instruction |
| b. | by checking interrupt register at the end of the fetch cycle |
| c. | whenever an interrupt is registered |
| d. | by checking interrupt register at regular time interval |
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Answer: (a).by checking interrupt register after execution of each instruction
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| 65. | What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below:
 |
| a. | 11 |
| b. | 10 |
| c. | 01 |
| d. | 00 |
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Answer: (d).00
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| 66. | Which one of the following set of gates is best suited for ‘parity’ checking and ‘parity’ generation? |
| a. | AND, OR, NOT |
| b. | NAND, NOR |
| c. | EX-OR, EX-NOR |
| d. | None of the above |
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Answer: (c).EX-OR, EX-NOR
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| 67. | What type of logic circuit is represented by the figure shown below?
 |
| a. | XOR |
| b. | XNOR |
| c. | XAND |
| d. | XNAND |
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Answer: (b).XNOR
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| 68. | The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio:
Where n → no. of tasks tn → time of completion of each task k → no. of segments of pipeline tp → clock cycle time S → speed up ratio  |
| a. | A |
| b. | B |
| c. | C |
| d. | D |
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Answer: (a).A
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| 69. | ................ refers to the discrepancy among a computed, observed or measured value and the true specified or theoretically correct values. |
| a. | Fault |
| b. | Failure |
| c. | Defect |
| d. | Error |
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Answer: (d).Error
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| 70. | Which logic family dissipates the minimum power ? |
| a. | DTL |
| b. | TTL |
| c. | ECL |
| d. | CMOS |
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Answer: (d).CMOS
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