41.  Using Booth's Algorithm for multiplication, the multiplier 57 will be recoded as 
a.  0 1 0 0 1 0 0 1 
b.  1 1 0 0 0 1 1 1 
c.  0 1 0 0 1 0 0 0 
d.  0 1 0 0 1 0 0 1 
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Answer: (a).0 1 0 0 1 0 0 1

42.  How many pulses are needed to change the contents of a 8bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)? 
a.  134 
b.  133 
c.  124 
d.  123 
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Answer: (d).123

43.  We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK flipflops required to implement this counter is 
a.  1 
b.  2 
c.  4 
d.  5 
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Answer: (c).4

44.  Consider a carry lookahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is 
a.  Θ(1) 
b.  Θ(Log (n)) 
c.  Θ(√ n) 
d.  Θ(n) 
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Answer: (b).Θ(Log (n))

45.  Consider an eightbit ripplecarry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _____________ 
a.  1 
b.  2 
c.  1 
d.  2 
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Answer: (a).1

46.  Let X be the number of distinct 16bit integers in 2’s complement representation. Let Y be the number of distinct 16bit integers in sign magnitude representation. Then X −Y is _________ 
a.  1 
b.  2 
c.  3 
d.  0 
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Answer: (a).1

47.  The addition of 4bit, two's complement, binary numbers 1101 and 0100 results in 
a.  0001 and an overflow 
b.  1001 and no overflow 
c.  0001 and no overflow 
d.  1001 and an overflow 
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Answer: (c).0001 and no overflow

48.  Which of the following input sequences for a crosscoupled RS flipflop realized with two NAND gates may lead to an oscillation ? 
a.  11, 00 
b.  01, 10 
c.  10, 01 
d.  00, 11 
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Answer: (d).00, 11

49.  The following bit pattern represents a floating point number in IEEE 754 single precision format 1 10000011 101000000000000000000000 The value of the number in decimal form is 
a.  10 
b.  13 
c.  26 
d.  None of these 
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Answer: (c).26

50.  A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be: 
a.  1, 1, 0 
b.  1, 0, 0 
c.  0, 1, 0 
d.  1, 0, 1 
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Answer: (b).1, 0, 0
